The present application generally relates to analog-to-digital conversion and, more particularly, to calibrating stages in pipeline analog-to-digital converters (ADCs) having multiple channels.
One efficient way to obtain a higher signal-to-noise ratio (SNR) in analog-to-digital conversion is to run two or more ADCs in parallel. The ADCs sample an input signal at the same instant, and their digital output data are summed. As discussed in PCT Publication No. WO 2011/018711 entitled ADC WITH ENHANCED AND/OR ADJUSTABLE ACCURACY, it has been shown that having two parallel ADCs can result in a 3 dB increase in SNR if the errors in the two ADCs are uncorrelated.
Calibration of ADCs is needed to obtain high accuracy and linearity. Offset errors, capacitor mismatch errors, and gain errors result in integral nonlinearity (INL) and differential nonlinearity (DNL) errors in ADCs. Various embodiments disclosed herein are directed to techniques for identifying and quantifying these errors for purposes of calibration. The techniques can be applied to an ADC architecture with two or more pipelined ADCs connected in parallel.